Impact of Technology Scaling on Digital Subthreshold Circuits

Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circuits is investigated. Migrating from 0.25-µm to 32-nm node is shown to considerably lower the energy consumption of a subthreshold 8×8-bit RCA multiplier. When reaching the smallest nodes, limitations come from slow scaling of the static energy consumption and the deteriorating static noise margin, which raises robustness issues when considering process variability. These effects result in a loss of energy efficiency. The use of non-minimum channel length is proposed to improve energy efficiency. At 32-nm node, it reduces total energy consumption by a factor 5.

• Type: Conference
• Year: 2008
• Where: ISVLSI
• Authors: David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
• Keywords: Energy Consumption, ISVLSI 2008, Static Energy Consumption, Subthreshold Circuits, VLSI