Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work proposes a GALS router with associated power control techniques, which enables low power SoC design. This is in contrast with previous works which centered attention in power reduction of SoC processing elements instead. The paper describes the asynchronous communication interface and the employed power control mechanism. The results obtained from simula...

• Type: Conference
• Year: 2008
• Where: ISVLSI
• Authors: Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans
• Keywords: Communication Architectures, ISVLSI 2008, Power Dissipation, Power Soc Design, VLSI