Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock fre

• Type: Conference
• Year: 2007
• Where: ISMVL
• Authors: Henning Gundersen, Yngvar Berg
• Keywords: Artificial Intelligence, Balanced Ternary, Balanced Ternary Notation, ISMVL 2007, Ternary Counters