Experimental Studies on SAT-Based ATPG for Gate Delay Faults

The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits – where multi-valued logic has to be considered – is studied and experimental results are reported.

• Type: Conference
• Year: 2007
• Where: ISMVL
• Authors: Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
• Keywords: Artificial Intelligence, Fault Model, Gate Delay Faults, Gate Size Decreases, ISMVL 2007