Efficient Modeling and Floorplanning of Embedded-FPGA Fabric

In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing for island style FPGAs using rectilinear macros. Several system integration issues are highlighted. Layout of a real life SOC with an embedded RTR FPGA for cryptographic applications, designed with this flow, is also presented.

• Type: Conference
• Year: 2007
• Where: FPL
• Authors: Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley
• Keywords: Embedded Rtr Fpga, FPGA, FPL 2007, Generic Fpga Modeling, Hardware