Sciweavers

DAC
2007
ACM
16 years 7 months ago
Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System
We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works ha...
Rebecca L. Collins, Luca P. Carloni
DAC
2007
ACM
16 years 7 months ago
Implicitly Parallel Programming Models for Thousand-Core Microprocessors
This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H....
DAC
2007
ACM
16 years 7 months ago
Novel CNTFET-based Reconfigurable Logic Gate Design
This paper describes a family of novel dynamically reconfigurable logic gates based on double-gate carbon nanotube field-effect transistors which demonstrate p-type or n-type switc...
David Navarro, Frédéric Gaffiot, Ian...
DAC
2007
ACM
16 years 7 months ago
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
Amith Singhee, Rob A. Rutenbar
160
Voted
DAC
2007
ACM
16 years 7 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
DAC
2007
ACM
16 years 7 months ago
The KILL Rule for Multicore
Multicore has shown significant performance and power advantages over single cores in commercial systems with a 2-4 cores. Applying a corollary of Moore's Law for multicore, ...
Anant Agarwal, Markus Levy
DAC
2007
ACM
16 years 7 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
DAC
2007
ACM
16 years 7 months ago
Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs
A key step in the design of cyclo-static real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure, which means that tasks...
Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit
161
Voted
DAC
2007
ACM
16 years 7 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...