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    145
    Voted
    DAC
    2007
    ACM
    127views Computer Architecture» more  DAC 2007»
    GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
    16 years 7 months ago
    GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
    Download  www.icims.csl.uiuc.edu
    In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
    Lei Cheng, Deming Chen, Martin D. F. Wong
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    DAC
    2007
    ACM
    150views Computer Architecture» more  DAC 2007»
    Chip Multi-Processor Generator
    16 years 7 months ago
    Chip Multi-Processor Generator
    Download  www.stanford.edu
    The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
    Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
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    174
    Voted
    DAC
    2007
    ACM
    123views Computer Architecture» more  DAC 2007»
    Shared Resource Access Attributes for High-Level Contention Models
    16 years 7 months ago
    Shared Resource Access Attributes for High-Level Contention Models
    Download  www.ece.vt.edu
    Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
    Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
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    DAC
    2007
    ACM
    115views Computer Architecture» more  DAC 2007»
    On-The-Fly Resolve Trace Minimization
    16 years 7 months ago
    On-The-Fly Resolve Trace Minimization
    Download  www.cs.tau.ac.il
    The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
    Ohad Shacham, Karen Yorav
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    DAC
    2007
    ACM
    99views Computer Architecture» more  DAC 2007»
    SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
    16 years 7 months ago
    SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
    Download  www.cse.cuhk.edu.hk
    The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
    Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
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    DAC
    2007
    ACM
    155views Computer Architecture» more  DAC 2007»
    Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
    16 years 7 months ago
    Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
    Download  homepages.cae.wisc.edu
    The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
    Zhuo Feng, Peng Li, Yaping Zhan
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    DAC
    2007
    ACM
    149views Computer Architecture» more  DAC 2007»
    DDBDD: Delay-Driven BDD Synthesis for FPGAs
    16 years 7 months ago
    DDBDD: Delay-Driven BDD Synthesis for FPGAs
    Download  www.icims.csl.uiuc.edu
    Lei Cheng, Deming Chen, Martin D. F. Wong
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    DAC
    2007
    ACM
    115views Computer Architecture» more  DAC 2007»
    Layered Switching for Networks on Chip
    16 years 7 months ago
    Layered Switching for Networks on Chip
    Download  web.it.kth.se
    We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
    Zhonghai Lu, Ming Liu, Axel Jantsch
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    192
    Voted
    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    16 years 7 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    DAC
    2007
    ACM
    134views Computer Architecture» more  DAC 2007»
    Synthesizing Stochasticity in Biochemical Systems
    16 years 7 months ago
    Synthesizing Stochasticity in Biochemical Systems
    Download  www.paradise.caltech.edu
    Randomness is inherent to biochemistry: at each instant, the sequence of reactions that fires is a matter of chance. Some biological systems exploit such randomness, choosing betw...
    Brian Fett, Jehoshua Bruck, Marc D. Riedel
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