0.5V 160-MHz 260uW all digital phase-locked loop

– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

• Type: Conference
• Year: 2009
• Where: DDECS
• Authors: Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
• Keywords: DDECS 2009, Digitally Controlled Oscillator, Hardware, Power All-digital Phase, Reference Clock Cycles