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DDECS
2009
IEEE
116views Hardware» more  DDECS 2009»
14 years 3 days ago
MTPP - Modular Traffic Processing Platform
High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware...
Jiri Halak, Sven Ubik
DDECS
2009
IEEE
129views Hardware» more  DDECS 2009»
14 years 2 months ago
Contactless characterization of MEMS devices using optical microscopy
András Timár, György Bogn&aacut...
DDECS
2009
IEEE
107views Hardware» more  DDECS 2009»
14 years 2 months ago
Effective mars rover platform design with Hardware / Software co-design
Gábor Marosy, Zoltán Kovacs, Gyula H...
DDECS
2009
IEEE
146views Hardware» more  DDECS 2009»
14 years 2 months ago
Enhanced LEON3 core for superscalar processing
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-o...
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A....
DDECS
2009
IEEE
149views Hardware» more  DDECS 2009»
14 years 2 months ago
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
Yiorgos Sfikas, Yiorgos Tsiatouhas
DDECS
2009
IEEE
95views Hardware» more  DDECS 2009»
14 years 5 months ago
Self-timed full adder designs based on hybrid input encoding
—Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are desc...
Padnamabhan Balasubramanian, D. A. Edwards, C. Bre...
DDECS
2009
IEEE
202views Hardware» more  DDECS 2009»
14 years 5 months ago
Asynchronous two-level logic of reduced cost
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
Igor Lemberski, Petr Fiser
DDECS
2009
IEEE
128views Hardware» more  DDECS 2009»
14 years 5 months ago
A fast untestability proof for SAT-based ATPG
—Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. Boolean solvers wor...
Daniel Tille, Rolf Drechsler
DDECS
2009
IEEE
111views Hardware» more  DDECS 2009»
14 years 5 months ago
0.5V 160-MHz 260uW all digital phase-locked loop
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hs...
DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
14 years 5 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards