Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits

Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise. Experiments show that our analytical predictions are at least two times better than the previous models in terms of the prediction accuracy. More precisely, experimental results show that the maximum error of our predictions is less than 10% while the average error is only 4%. Finally, based on the proposed analytical models, we discuss the effects of transistor sizing and buffering on crosstalk noise reduction in VLSI circuits.

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Payam Heydari, Massoud Pedram
• Keywords: Crosstalk Noise, Crosstalk Noise Reduction, Hardware, ICCD 2001, Micron Vlsi Circuits