IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
IEEEPACT
2009
IEEE
13 years 10 months ago
2009
IEEE
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Abstract—This paper proposes a new software-oriented approach for managing the distributed shared L2 caches of a chip multiprocessor (CMP) for latency-oriented multithreaded appl...