ATPG for Heat Dissipation Minimization During Scan Testing

An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of low power circuits and bare die that would otherwise require expensive heat removal equipment for testing at high speeds. The proposed ATPG exploits all don’t cares that occur during scan shifting, test application, and responsecapture to minimize switching activity in the circuit under test. Furthermore, an ATPG that maximizes the number of state inputs that are assigned don’t care values, has been developed. The proposedtechniquehas beenimplementedand usedto generatetests for full scan versions of ISCAS 89 benchmark circuits. These tests decrease the average number of transitions during test by 19% to 89%, when comparedwith those generatedby a simple PODEM implementation.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Seongmoon Wang, Sandeep K. Gupta
• Keywords: Computer Architecture, DAC 1997, Expensive Heat Removal, Low Power Circuits, Sequential Circuits