Boolean Function Representation Using Parallel-Access Diagrams

Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually related to deterministic finite automata (DFA), accepting the language formed by the minterms of a function. This analogy suggests the use of nondeterministic devices as language recognizers. Unlike ROBDDs, the diagrams introduced in this paper allow multiple outgoing edges with the same label. By suitably restricting the degree of nondeterminism, we still obtain a canonical form for logic functions. Using PADs, we are able to reduce the memory occupation with respect to traditionalROBDDs for several benchmark functions. Moreover, the analysis of the PAD graphs allowed us to sometimes identify new and better variable ordering for several benchmark circuits.

• Type: Conference
• Year: 1996
• Where: GLVLSI
• Authors: Valeria Bertacco, Maurizio Damiani
• Keywords: Binary Decision Diagrams, Deterministic Finite Automata, GLVLSI 1996, Logic Functions, VLSI