ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper describes the tools, techniques, and devices used to design embedded products with system
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
ISCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
ISCA
2006
IEEE
14 years 8 months ago
2006
IEEE
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
ISCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
ISCA
2006
IEEE
14 years 8 months ago
2006
IEEE
A simple and low-cost approach to supporting snoopy cache coherence is to logically embed a unidirectional ring in the network of a multiprocessor, and use it to transfer snoop me...