A capacitive coupling interface with high sensitivity for wireless wafer testing

—A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver converts the data with various logic thresholds to that with optimum logic threshold. The receiver with the optimum logic threshold achieves the highest sensitivity of 25 mV at the data rate of 2 Gb/s in 0. 18 µm CMOS. The proposed receiver increases the communication distance over 4 times while providing tolerance against the distance-voltage-area variations.

• Type: Conference
• Year: 2009
• Where: 3DIC
• Authors: Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
• Keywords: 3DIC 2009, Hardware, Logic Threshold, Optimum Logic Threshold, Various Logic Thresholds