Characterisation of FPGA Clock Variability

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic overdesign. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FPGAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation.

• Type: Conference
• Year: 2008
• Where: ISVLSI
• Authors: N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung
• Keywords: Clock Skew, ISVLSI 2008, Path Delay Variation, Performance Variation, VLSI