Sciweavers

INFOCOM
2012
IEEE
12 years 1 months ago
Energy-optimal mobile application execution: Taming resource-poor mobile devices with cloud clones
Abstract—In this paper, we propose to leverage cloud computing to tame resource-poor mobile devices. Specifically, mobile applications can be executed in the mobile device (know...
Yonggang Wen, Weiwen Zhang, Haiyun Luo
ESSCIRC
2011
93views more  ESSCIRC 2011»
12 years 11 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
TCAD
2008
93views more  TCAD 2008»
13 years 11 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
CF
2008
ACM
14 years 1 months ago
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components--including registers, function...
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, ...
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
14 years 3 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...
ASPDAC
2007
ACM
87views Hardware» more  ASPDAC 2007»
14 years 3 months ago
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools
- A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock freque...
Fu-Ching Yang, Ing-Jer Huang
RTSS
1998
IEEE
14 years 3 months ago
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
Inki Hong, Gang Qu, Miodrag Potkonjak, Mani B. Sri...
MICRO
2000
IEEE
86views Hardware» more  MICRO 2000»
14 years 3 months ago
On pipelining dynamic instruction scheduling logic
A machine’s performance is the product of its IPC (Instructions Per Cycle) and clock frequency. Recently, Palacharla, Jouppi, and Smith [3] warned that the dynamic instruction s...
Jared Stark, Mary D. Brown, Yale N. Patt
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
14 years 5 months ago
Hardware implementation of super minimum all digital FM demodulator
– We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique ...
Nursani Rahmatullah, Arif E. Nugroho