Design For Testability Method for CML Digital Circuits

This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitors all gate output swings and flags all abnormal voltage excursions. These detectors cover classes of faults that cannot be tested by stuck-at testing methods only. Circuit simulations have shown that abnormal gate output excursions caused by the presence of a defect are common with CML. We also show that this technique works well below "at-speed" frequencies. Finally, variants of the built-in detectors with reduced area overhead are proposed.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham
• Keywords: Abnormal Voltage Excursions, Built-in Detectors, DATE 1999, Gate Output, Hardware