Dynamic Flip-Flop with Improved Power

An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the tpLH and tpHL of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.

• Type: Conference
• Year: 2000
• Where: ICCD
• Authors: Nikola Nedovic, Vojin G. Oklobdzija
• Keywords: Dynamic Flip-flop, Hardware, ICCD 2000, Insignificant Area Increase, Logic Embedding Property