A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay.

• Type: Conference
• Year: 2007
• Where: ISQED
• Authors: Toshinori Sato, Yuji Kunitake
• Keywords: Canary Logic, Hardware, ISQED 2007, Typical-case Design, Typical-case Design Methodologies