An efficient procedure for the synthesis of fast self-testable controller structures

The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced, and the fault coverage and system speed can be enhanced. The presented algorithm constructs realizations of a given finite state machine specification which can be trivially implemented by a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhea...

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Sybille Hellebrand, Hans-Joachim Wunderlich
• Keywords: Additional Test Register, Fault Coverage, Hardware, ICCAD 1994, Self-testable Pipeline-like Controller