Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics

Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive. In this paper, we discuss some recent novel schemes for extraction and reduced order modeling that help overcome this computational bottleneck.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Peter Feldmann, Sharad Kapur, David E. Long
• Keywords: Computationally Expensive, DATE 1999, Hardware, Modern Ic Design, Reduced Order Modeling