Estimation of Bus Performance for a Tuplespace in an Embedded Architecture

This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristics of typical embedded architectures for factory automation. We describe the features of a bus for embedded applications and the problem of estimating its performance, and present a rapid prototyping design methodology developed for a qualitative and quantitative estimation. The methodology is based on a mix of different modeling languages such as Java, C++, SystemC and Network Simulator2 (NS2). Its application allows to estimate the expected performance of the bus under design in relation to the developed tuplespace.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
• Keywords: DATE 2003, Design Methodology, Factory Automation, Hardware, Typical Embedded Architectures