Evaluating register file size in ASIP design

Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performance. Keywords Register file, Synthesis, Instruction set, Instruction power model, Register spill, Application specific instruction set processor

• Type: Conference
• Year: 2001
• Where: CODES
• Authors: Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan
• Keywords: Application Specific Instruction Set Processor, CODES 2001, Register File, Register File Size, Software Engineering