Exploiting Input Variations for Energy Reduction

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. They enable to eliminate design margins as well as to tolerate parameter variations. We are investigating canary logic, which we proposed as a promising technique that enables the typical-case design. Currently, we utilize the canary logic for power reduction by exploiting input variations, and its potential of 30% power reduction in adders has been estimated at gate-level simulations. In this paper, we evaluate how canary logic is effective for power reduction of the entire microprocessor and find 9% energy reduction.

• Type: Conference
• Year: 2007
• Where: PATMOS
• Authors: Toshinori Sato, Yuji Kunitake
• Keywords: Canary Logic, Design Margins, PATMOS 2007, Power Reduction, Simulation