Exploiting regularity for low-power design

Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements -- buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the regularity and common computational patterns in the algorithm to reduce the fan-outs and fan-ins of the interconnect wires, resulting in reduced bus capacitances and a simplified interconnect structure. Average power savings of 47% and 49% in buses and multiplexors, respectively, are demonstrated on a set of benchmark examples.

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Renu Mehra, Jan M. Rabaey
• Keywords: Hardware, ICCAD 1996, Interconnect, Simplified Interconnect Structure, Techniques Produce Architectures