Fault Injection for Verifying Testability at the VHDL Level

This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: S. R. Seward, Parag K. Lala
• Keywords: Fault Injection Block, Hardware, ITC 2003, Technique Allows Incorporation, VHDL Level