ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper prese...
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of...
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...