Sciweavers

DATE
2010
IEEE

Formal verification of analog circuits in the presence of noise and process variation

14 years 3 months ago
Formal verification of analog circuits in the presence of noise and process variation
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose to use stochastic differential equations (SDE) to model the designs. We find a closed form solution for the SDEs, then integrate the device variation due to the 0.18
Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zak
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 2010
Where DATE
Authors Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zaki, Sofiène Tahar, Lawrence C. Paulson
Comments (0)