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    GLVLSI
    1996
    IEEE
    102views VLSI» more  GLVLSI 1996»

    FPGA-based high performance page layout segmentation

    14 years 3 months ago
    FPGA-based high performance page layout segmentation
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    Nalini K. Ratha, Anil K. Jain, Diane T. Rover
    claim paper
    Added 07 Aug 2010
    Updated 07 Aug 2010
    Type Conference
    Year 1996
    Where GLVLSI
    Authors Nalini K. Ratha, Anil K. Jain, Diane T. Rover
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