Functional test generation using property decompositions for validation of pipelined processors

Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While existing model checking based approaches have proposed several promising ideas for efficient test generation, many challenges remain in applying them to realistic pipelined processors. The time and resources required for test generation using existing model checking based techniques can be extremely large. This paper presents an efficient test generation technique using decompositional model checking. The contribution of the paper is the development of both property and design decomposition procedures for efficient test generation of pipelined processors. Our experimental results using a multi-issue MIPS processor demonstrate several orders-of-magnitude reduction in memory requirement and test generation time.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Heon-Mo Koo, Prabhat Mishra
• Keywords: DATE 2006, Efficient Test Generation, Hardware, Model Checking, Test Generation