A Genetic Testing Framework for Digital Integrated Circuits

In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e., register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage.

• Type: Conference
• Year: 2002
• Where: ICTAI
• Authors: Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick
• Keywords: Artificial Intelligence, Functional Test Generation, ICTAI 2002, Register Transfer, Test Generation