Global interconnect sizing and spacing with consideration of coupling capacitance

This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in addition to area and fringing capacitances. We introduce the formulation of symmetric and asymmetric wire sizing and spacing. We prove two important results on the symmetric and asymmetric effective-fringing properties which lead to a very effective bound computation algorithm to compute the upper and lower bounds of the optimal wire sizing and spacing solution for all nets under consideration. Our experiments show that the upper and lower bounds often meet quickly or become close after a few iterations for most wire segments. When the lower and upper bounds do not meet, we then apply a bottom-up dynamic programming-based refinement algorithm to compute the final wire sizing and spacing solution for each net. To our knowledge, this is the first in-depth study of global wire sizing and spa...

• Type: Conference
• Year: 1997
• Where: ICCAD
• Authors: Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
• Keywords: Hardware, ICCAD 1997, Lower Bounds, Sizing, Wire