A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm

In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35? CMOS technology resulted in a throughput of 232Mbps for iterative

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty
• Keywords: Area Efficient Architecture, Computer Architecture, Rijndael Algorithm, VLSID 2006