Improved clock-gating through transparent pipelining

This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 4060% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput. Categories and Subject Descriptors

• Type: Conference
• Year: 2004
• Where: ISLPED
• Authors: Hans M. Jacobson
• Keywords: Clock, Clock Gating, Clock Power, ISLPED 2004