ICCAD
2009
IEEE
13 years 9 months ago
2009
IEEE
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
ISLPED
2004
ACM
14 years 4 months ago
2004
ACM
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DAC
2003
ACM
15 years 12 days ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...