CORR
2010
Springer
13 years 11 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
ISLPED
2000
ACM
14 years 3 months ago
2000
ACM
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
FPL
2009
Springer
14 years 4 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
ISLPED
2004
ACM
14 years 4 months ago
2004
ACM
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
PATMOS
2005
Springer
14 years 5 months ago
2005
Springer
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
ISPASS
2005
IEEE
14 years 5 months ago
2005
IEEE
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...
DATE
2006
IEEE
14 years 5 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
ISVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
ISCAS
2007
IEEE
14 years 5 months ago
2007
IEEE
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinus...
CODES
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...