Instruction packing: reducing power and delay of the dynamic scheduling logic

The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for the execution. Traditional designs use one issue queue entry for each instruction, regardless of the actual number of operands actively used in the wakeup process. In this paper we propose Instruction Packing – a novel microarchitectural technique that reduces both the delay and the power consumption of the issue queue by sharing the associative part of an issue queue entry between two instructions, each with at most one non-ready register source operand at the time of dispatch. Our results show that Instruction Packing provides a 39% reduction of the whole issue queue power

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
• Keywords: ISLPED 2005, Issue Queue, Issue Queue Entries, Issue Queue Entry