Leakage power modeling and optimization in interconnection networks

Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 9598% accuracy against HSPICE estimates. When applied to interconnection networks, combined with previous proposed dynamic power models, we gain valuable insights on total network power consumption. Our modeling shows router buffers to be a prime candidate for leakage power optimization. We thus investigate the design space of power-aware buffer policies, propose a suite of policies, and explore the impact of various circuits mechanisms on these policies . Simulations show power-aware buffers saving up to 96.6% of total buffer leakage power. Categories and Subject Descriptors C.2.1 [Computer-Communication Networks]: Network architecture and design General Terms Measurement, Design Keywords Leakage power, interconnection networks, power optimization

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Xuning Chen, Li-Shiuan Peh
• Keywords: Architectural Leakage Power, Interconnection Networks, ISLPED 2003, Leakage Power