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ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 7 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
CASES
2008
ACM
14 years 1 months ago
Design space exploration for field programmable compressor trees
The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device....
Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero,...
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
14 years 3 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
FPGA
1997
ACM
145views FPGA» more  FPGA 1997»
14 years 3 months ago
Generation of Synthetic Sequential Benchmark Circuits
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
14 years 3 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
ISCAS
1999
IEEE
85views Hardware» more  ISCAS 1999»
14 years 3 months ago
Equivalence classes of clone circuits for physical-design benchmarking
To provide a better understanding of physical design algorithms and the underlying circuit architecture they are targeting, we need to exercise the algorithms and architectures wi...
Michael D. Hutton, Jonathan Rose
ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
14 years 3 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
ASPDAC
1999
ACM
151views Hardware» more  ASPDAC 1999»
14 years 3 months ago
Benchmark Circuits Improve the Quality of a Standard Cell Library
-- The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It isfound that most of the errors can be uncover...
Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
14 years 5 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
ICCAD
2004
IEEE
123views Hardware» more  ICCAD 2004»
14 years 8 months ago
Logical effort based technology mapping
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
Shrirang K. Karandikar, Sachin S. Sapatnekar