Low power DCT implementation approach for VLSI DSP processors

This paper presents an algorithm for the low power implementation of the Discrete Cosine Transform on Single multiplier CMOS DSPs. The algorithm reduces power by a combination of using shift operations, where possible, and manipulatingbit-correlation between successive cosine coefficients applied to the input of the multiplier section such that the effective switched capacitance is reduced. This reduces the switching activity in the multiplication of a Discrete Cosine Transform processor. The paper describes the algotrithm, the evaluation procedure and presents results with a number of example images illustratingupto 50 power savings.

• Type: Conference
• Year: 1999
• Where: ISCAS
• Authors: S. Masupe, T. Arslan
• Keywords: Discrete Cosine Transform, Hardware, ISCAS 1999, Multiplier Cmos Dsps, Successive Cosine Coefficients