Maurer computers for pipelined instruction processing

We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a new mathematical approach to model micro-architectures and to verify their correctness and anticipated speed-up results.

• Type: Journal
• Year: 2008
• Where: MSCS
• Authors: Jan A. Bergstra, C. A. Middelburg
• Keywords: Instruction Processing, Maurer Machines, MSCS 2008, Non-pipelined Instruction Processing