26 search results - page 1 / 6 » Maurer computers for pipelined instruction processing |
MSCS
2008
13 years 7 months ago
2008
We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We sho...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
ICS
1989
Tsinghua U.
13 years 11 months ago
1989
Tsinghua U.
Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instru...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...