NBTI-aware flip-flop characterization and design

With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, different types of flip-flops exhibit different levels of susceptibility to NBTI-induced change in their setup/hold time values. Finally, an NBTI-aware transistor sizing technique can minimize the NBTI effect on timing characteristics of the flip-flops. Categories and Subject Descriptors: B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids. General Terms: Performance, Design, Reliability.

• Type: Conference
• Year: 2008
• Where: GLVLSI
• Authors: Hamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram
• Keywords: Flip-flops, GLVLSI 2008, Negative Bias Temperature Instability, Transistor Aging Process, VLSI