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Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
Amir Moradi, Thomas Eisenbarth, Axel Poschmann, Ch...
We survey a set of flip-flops designed for low power and high performance. We highlight the basic features of these flip-flops and evaluate them based on timing characteristics, po...
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
Hamed Abrishami, Safar Hatami, Behnam Amelifard, M...
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...