ICISC
2009
14 years 26 days ago
2009
Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic...
CDES
2006
14 years 4 months ago
2006
We survey a set of flip-flops designed for low power and high performance. We highlight the basic features of these flip-flops and evaluate them based on timing characteristics, po...
ASPDAC
2006
ACM
14 years 6 months ago
2006
ACM
GLVLSI
2008
IEEE
14 years 9 months ago
2008
IEEE
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
GLVLSI
2008
IEEE
14 years 9 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
DFT
2009
IEEE
14 years 10 months ago
2009
IEEE
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
ISQED
2010
IEEE
14 years 10 months ago
2010
IEEE
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...