Networks on Chips: from research to products

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation. Categories and Subject Descriptors B.4.3 [INPUT/OUTPUT AND DATA COMMUNICATIONS]: Interconnections (Subsystems)—topology General Terms Design Keywords Network on Chip, NoC, System on Chip, SoC

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini
• Keywords: Chip-level Interconnect Problem, Computer Architecture, DAC 2010, Input/Output And Data, Power Consumption Levels