A power estimation methodology for systemC transaction level models

Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With the presence of complex cores in current day embedded system-on-chip devices, the problem of complete system level power estimation is gaining significance. Transaction level models for SoCs are gaining increasing attention with emerging architectural modeling standards like SystemC. In this paper we present a methodology for performing system power estimation for different scenarios or applications being executed on these transaction level models. We describe techniques and a setup for transaction level power characterization, and an approach to augment SystemC transaction level models to perform transaction level power estimation. We also present experimental results to validate the accuracy and speed of our approach. Categories and Subject Descriptors: J.6 [Computer-aided design]; B.7.2 [Integrated circuits]...

• Type: Conference
• Year: 2005
• Where: CODES
• Authors: Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
• Keywords: CODES 2005, Hardware-Software Codesign, Level Power Estimation, Transaction Level, Transaction Level Models