TCAD
2008
13 years 11 months ago
2008
We propose a methodology for the early estimation of communication implementation choices eftarting from an abstract transaction level system model (TLM). The reference version of ...
ASPDAC
2009
ACM
14 years 4 months ago
2009
ACM
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
DATE
2003
IEEE
14 years 4 months ago
2003
IEEE
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
CODES
2005
IEEE
14 years 5 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
ISQED
2006
IEEE
14 years 5 months ago
2006
IEEE
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
CODES
2008
IEEE
14 years 6 months ago
2008
IEEE
In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
DAC
2006
ACM
15 years 12 days ago
2006
ACM
In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have ana...