A programmable built-in self-test core for embedded memories

Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a programmable built-in self-test (BIST) design that is used for testing embedded memories, especially DRAMs. The BIST chip supports various memory test algorithms by a novel controller and sequencer design. The area of the core circuit is about 1, 020

• Type: Conference
• Year: 2000
• Where: ASPDAC
• Authors: Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
• Keywords: ASPDAC 2000, BIST Chip, Hardware, Programmable Built-in Self-test, Testing Embedded Memories