Rate Optimal VLSI Design from Data Flow Graph

This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts buffer registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if exists, than overlapped schedules.

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Moonwook Oh, Soonhoi Ha
• Keywords: Computer Architecture, DAC 1998, Rate Optimal Scheduling, Rate Optimal Vlsi, VLSI Design